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EECE.6540 Heterogeneous Computing (University of Massachusetts Lowell) - 46. Basic FPGA concepts
46. Basic FPGA concepts
This video covers basic concepts of field programmable gate arrays (FPGAs). Unlike CPUs, FPGAs can be programmed to fit specific hardware resources meaning they are highly customizable. The video discusses the importance of latency in circuit design and how it can be balanced with maximizing f max. It introduces the concept of pipeline design to increase the frequency at which a computation can be performed, as well as discussing data paths and control paths in a circuit. Finally, the video discusses circuit occupancy in an FPGA and how decreasing bubbles and increasing occupancy can increase f max.
47. Design Analysis (I): Analyze FPGA Early Images
47. Design Analysis (I): Analyze FPGA Early Images
This section of the video focuses on the process of analyzing FPGA early images for a DPC++ design. The speaker explains the steps involved, such as compiling the program, generating FPGA binary, and running profiling. The video includes a demo of how to generate reports and interpret the various information panels provided in the reports. The speaker also analyzes the FPGA early images of a b2 module and discusses the various logic blocks, loops, load unit, and unroll factor. They also discuss how the design of a kernel function can significantly impact the internal design on FPGA and provide examples of how the inner and outer loops can be unrolled to increase throughput. The examples illustrate the flexibility of high-level language programming in influencing the FPGA's hardware resources.
48. DPC++ FPGA Design Analysis (II): Runtime Profiling
48. DPC++ FPGA Design Analysis (II): Runtime Profiling
In this video, the presenter discusses the process of analyzing a program's runtime performance using tools that collect performance data by adding profiling instrument registers to the FPGA bit streams. They demonstrate how to compile for profiling and interpret the collective profiling results using the Intel FPGA dynamic profiler with user-added performance counters. They show how the V2 profiler displays kernel functions and executables used for analyzing runtime profiling results, and how to identify partition bottlenecks and optimize them. The example used is a matrix modification kernel that had a lot of memory accesses to global memory, which was optimized by using local memory to reduce communication with global memory and improve design efficiency.
EECE.6540 Heterogeneous Computing (University of Massachusetts Lowell) - 49. OpenCL Examples
49. OpenCL Examples (I)
The YouTube video "OpenCL Examples (I)" covers the implementation of matrix multiplication using nested loops in C programming, and its implementation as an OpenCL kernel. The lecturer explains how to use two levels of nested loops for the dot product calculation of the resulting element in the matrix, and how each output element of matrix C is treated as a separate work item in OpenCL. The video also covers the steps required to prepare the OpenCL kernel for execution and retrieve the resulting matrix from a device to a host, as well as setting work group sizes and executing the kernel with modified kernel arguments. Additionally, a sample code for matrix multiplication is provided, and the speaker demonstrates the process of obtaining device and platform IDs on a Mac OS and creating a program object on different platforms. Lastly, the video explains buffer management, tracing the resources allocated on the host side and OpenCL resources used, and provides a simple multiplication kernel example.
This video covers various examples of using OpenCL, including matrix multiplication, image rotation, and image filtering. For image rotation, the speaker explains how to break down the problem using input decomposition and demonstrates the kernel function used to identify the original and new location of each pixel. For image filtering, the speaker discusses the concept of creating image objects on the device side and the use of OpenCL sampler to define how to access the image. They also present a sample implementation of the image convolution function with two nested for loops. The video concludes with a demonstration of using OpenCL to perform a convolution filter on an image and verifying the results.
A Comparison of SYCL, OpenCL, CUDA, & OpenMP for Massively Parallel Support Vector Classification (WOCL / SYCLcon 2022)
A Comparison of SYCL, OpenCL, CUDA, & OpenMP for Massively Parallel Support Vector Classification
The video compares the performance of SYCL, OpenCL, CUDA, and OpenMP on different hardware platforms for massively parallel support vector machine classification. The speaker explains the parallelization of matrix-vector multiplication with an implementation called Parallel Fibonacci, which supports multigpu execution, but only binary classification and dense calculations. The hardware used for testing includes Nvidia A100 and RTX 380 GPUs, AMD Radeon Pro 7 GPU, and Intel Core E9-10-09020X CPU. Results show that CUDA is the fastest backend for Nvidia GPUs, while OpenCL is the fastest backend for CPUs. SYCL is user-friendly, while Hipsicle is faster than DPC++ and OpenCL for cheap use. Additionally, the speaker discusses future work, such as investigating performance on FPGAs, adding support for distributed systems via MPIs, and using mixed precision calculations and special machine learning hardware like NVIDIA’s tensor cores.
Reaching Even Richer C++ in OpenCL Kernels with use of libclcxx (WOCL / SYCLcon 2022)
Reaching Even Richer C++ in OpenCL Kernels with use of libclcxx
The video discusses the use of libclcxx to enable the integration of C++ libraries into open source kernel development. The project integrates type traits, an essential library for meta programming in C++, with the goal of exposing more C++ functionality to developers. The video showcases how the type traits library can optimize the performance of OpenCL kernels through its ability to manipulate address space and vector types. The video encourages developers to experiment with the library and contribute to reducing development cycles while obtaining maximum compatibility with C++. The library provides oxygen documentation in a similar style to the C++ reference pages, making it easy for developers to navigate through the new functionality.
SYCL beyond OpenCL: The architecture, current state and future direction of hipSYCL (IWOCL / SYCLcon 2020)
SYCL beyond OpenCL: The architecture, current state and future direction of hipSYCL
The hipSYCL project is an open-source implementation of SYCL that targets GPUs through the HIP programming model instead of OpenCL. It consists of a compiler component, sickle interface, and secure runtime. The secure compiler identifies kernels, handles local memory allocation, and implements a signaling mechanism. The dispatch function creates specific items based on user-provided kernels, and optimized functions can be defined with rock prim. The future direction is to allow for multiple back-ends and remove restrictions on the static compilation model. The operation submission model is transitioning to a batch submission for higher task throughput, and hipSYCL is interoperable at the source code level, enabling mixing and matching with hip and CUDA. As an open-source project, contributors are welcome.
SYCL: the future is open, parallel and heterogenous (Core C++ 2022)
SYCL: the future is open, parallel and heterogenous
In this video about SYCL programming, the speaker highlights the need to go up the abstraction level to increase productivity and attract more developers, as complex models require increased compute power, which is met by accelerator systems. The importance of software portability and OneAPI is emphasized, as it allows devices to work on CPUs, GPUs, and other devices. The benefits of SYCL, an open, parallel, and heterogeneous programming model, are also discussed, with the speaker highlighting the numerous online resources and tools available to optimize code and improve performance. The speaker encourages viewers to visit oneapi.io and their YouTube channel for resources and support.
GPU acceleration in Python
GPU acceleration in Python
The video explains how to achieve GPU acceleration in Python programming by leveraging the power of graphics processing units, which can provide a speedup of up to 10x with data parallelism. The two standards for GPU computing, OpenCL and CUDA, are briefly introduced, and the video demonstrates the use of Pi OpenCL and CUDA for matrix multiplication in Python. The speaker explains the use of global memory and the kernel for matrix multiplication, and also discusses the algorithm used for computing one element in the matrix-matrix product. The code for GPU acceleration in C and Python is discussed, with emphasis on understanding internal representations of matrices and memory allocation. The exercises in the lecture provide a basis for further exploration of GPU computing.
OpenCL 3.0 Launch Presentation (IWOCL / SYCLcon 2020)
OpenCL 3.0 Launch Presentation
The launch of OpenCL 3.0 is discussed in this video, with a focus on its importance for low-level parallel programming in the industry. OpenCL 3.0 does not add new functionality to the API, but provides an ecosystem realignment to enable OpenCL to reach more developers and devices. The presenter also discusses the addition of extensions for DSP light processors, the roadmap for future functionality, and the growing ecosystem of open-source kernel language compilers that can generate spirit kernels for OpenCL Vulcan. Feedback from users is encouraged to help finalize the spec as the working group prepares for the first wave of implementations over the next few months.